(a) Field of the Invention
The present invention relates to a method for patterning an insulator film by a direct writing technique using electron beam irradiation and, more particularly, to a method for patterning an insulator film while effectively preventing charge-up by electrons during the direct writing step using the electron beam irradiation.
(b) Description of the Related Art
Exposure processes in the fabrication of a semiconductor device are categorized roughly into two groups including a pattern transfer technique wherein a pattern formed on a mask is transferred onto a photoresist film by using light or X-Rays, and a direct writing technique wherein a pattern is directly written based on a design onto a resist film by using an electron beam.
In the direct writing technique, if grounding of the wafer or substrate is incomplete during irradiation of the electron beam onto an insulator film on the wafer, a charge-up of electrons occurs wherein electrons are accumulated on the interface between the wafer and the insulator film. The charge-up causes deflection of the electron beam during the irradiation thereof to deform the resultant pattern, which impedes the direct writing technique from providing a fine pattern.
FIG. 1 shows a conventional technique for grounding a wafer during the direct writing process using an electron beam. The wafer 11 is grounded by thrusting a grounding pin 17 having a sharp tip onto the wafer 11 with a moderate force that allows the grounding pin 17 to penetrate a resist film 13 and an insulation film (SiO.sub.2 film) 12 and to contact with the wafer 11 without causing any dust around the wafer. However, in a semiconductor device having multi-level interconnect layers, it is difficult to assure a complete grounding of the wafer by the grounding pin 17 during patterning of a top insulator layer, thereby being unable to effectively suppress the problem charge-up.
Patent Publication JP-A-1-220441 proposes an improved direct writing technique which suppresses the charge-up in a multi-level interconnection structure of a semiconductor device. In the proposal, a portion of the underlying insulator layers at which the grounding pin is to penetrate the insulator layers is selectively removed by a photolithographic technique using a first resist film before forming a second resist film through which the grounding pin penetrates to contact the substrate during patterning a top insulator film. This technique allows easy penetration by the grounding pin for contact with the substrate.
The proposed direct writing technique, however, uses the step of removing the portion of the underlying layers as an additional step, which decreases the throughput of the direct writing.